PrototypeCommon
hell03end/verilog-uart
Simple 8-bit UART realization on Verilog HDL.
Archived: this repository is read-only
- Owner
- hell03end (personal account)
- Stars
- Stars: 121
- Forks
- Forks: 21
- Language
- Verilog
- License
- MIT
- Created
- 2018
- Topics
- veriloghdlquartusuartfpga
- Tier
- Prototype (100 to 249 ★) What this tier means
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