PrototypeCommon
jasonlin316/RISC-V-CPU
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
- Owner
- jasonlin316 (personal account)
- Stars
- Stars: 153
- Forks
- Forks: 28
- Language
- Verilog
- License
- None
- Created
- 2019
- Topics
- risc-vriscv32gate-levelplace-and-routevectorprocessorchiptape-outverilog
- Tier
- Prototype (100 to 249 ★) What this tier means
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