Illustration drawn by RepoMasters from the repo’s ID and its language color. Credits
PrototypeCommon

karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2

A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator

Owner
karthisugumar (personal account)
Stars
Stars: 187
Forks
Forks: 30
Language
SystemVerilog
License
None
Created
2019
Tier
Prototype (100 to 249 ★) What this tier means
View on GitHub

Nearby in SystemVerilog

All SystemVerilog repos