PrototypeCommon
lakshmi-sathi/avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
- Owner
- lakshmi-sathi (personal account)
- Stars
- Stars: 126
- Forks
- Forks: 40
- Language
- No language
- License
- GPL-2.0
- Created
- 2020
- Topics
- pllclock-multiplierintellectual-propertyanalog-circuitphase-detectorcharge-pumprtl2gdsmanufacturableicasic
- Tier
- Prototype (100 to 249 ★) What this tier means