PrototypeCommon
meiniKi/FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
- Owner
- meiniKi (personal account)
- Stars
- Stars: 124
- Forks
- Forks: 9
- Language
- SystemVerilog
- License
- None
- Created
- 2024
- Topics
- computer-architecturedigital-designembedded-systemsfpgarisc-vsystem-on-chipvlsi-design
- Tier
- Prototype (100 to 249 ★) What this tier means
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