Illustration drawn by RepoMasters from the repo’s ID and its language color. Credits
PrototypeCommon

nxbyte/ARM-LEGv8

Verilog Implementation of an ARM LEGv8 CPU

Owner
nxbyte (personal account)
Stars
Stars: 113
Forks
Forks: 30
Language
Verilog
License
MIT
Created
2018
Topics
veriloghennessypattersonarm-legv8-simulatorarmisapipeline-cpuhazard-detectionforwarding-unitsingle-cycle
Tier
Prototype (100 to 249 ★) What this tier means
View on GitHub

More repos by nxbyte

All 2 repos by nxbyte

Nearby in Verilog

All Verilog repos