PrototypeCommon
peilin-chen/Zhulong-RISCV-CPU
CPU Design Based on RISCV ISA
- Owner
- peilin-chen (personal account)
- Stars
- Stars: 148
- Forks
- Forks: 25
- Language
- Verilog
- License
- MIT
- Created
- 2024
- Topics
- integrated-circuitsprocessor-design
- Tier
- Prototype (100 to 249 ★) What this tier means
Nearby in Verilog
All Verilog repos- michaelehab/AES-VerilogStars: 149VerilogPrototype
- WangXuan95/FPGA-NFCStars: 148VerilogPrototype
- geohot/gpunoobStars: 148VerilogPrototype
- openpower-cores/a2oStars: 147VerilogPrototype
- neelkshah/MIPS-ProcessorStars: 146VerilogPrototype