PrototypeCommon
stnolting/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Archived: this repository is read-only
- Owner
- stnolting (personal account)
- Stars
- Stars: 101
- Forks
- Forks: 15
- Language
- VHDL
- License
- BSD-3-Clause
- Created
- 2022
- Topics
- asicfpgaghdlneorv32verilogicarus-verilog
- Tier
- Prototype (100 to 249 ★) What this tier means
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