RCEpic
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
- Owner
- ucb-bar (organization)
- Stars
- Stars: 2,445
- Forks
- Forks: 933
- Language
- Scala
- License
- BSD-3-Clause
- Created
- 2016
- Topics
- rocket-chipchip-generatorchiselriscvrtlsocperipheralschipyardrisc-vboom
- Tier
- RC (2,000 to 4,999 ★) What this tier means
More repos by ucb-bar
All 21 repos by ucb-bar- ucb-bar/gemminiStars: 1,544ScalaBeta
- ucb-bar/chisel-tutorialStars: 759ScalaBeta
- ucb-bar/riscv-sodorStars: 758ScalaBeta
- ucb-bar/riscv-miniStars: 620ScalaAlpha
- ucb-bar/fpga-zynqStars: 425TclAlpha
- ucb-bar/berkeley-hardfloatStars: 394ScalaAlpha
Nearby in Scala
All Scala repos- geekyouth/SZT-bigdataStars: 2,472ScalaRC
- typelevel/fs2Stars: 2,456ScalaRC
- metarank/metarankStars: 2,455ScalaRC
- NotProtonNot/NotProtonStars: 2,382ScalaRC
- apache/kyuubiStars: 2,376ScalaRC
- scalameta/metalsStars: 2,337ScalaRC