PrototypeCommon
wyvernSemi/pcievhost
PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
- Owner
- wyvernSemi (personal account)
- Stars
- Stars: 155
- Forks
- Forks: 35
- Language
- C
- License
- GPL-3.0
- Created
- 2016
- Topics
- pciemodellingverilogverificationbfmvirtualcosimcplighdl
- Tier
- Prototype (100 to 249 ★) What this tier means
Nearby in C
All C repos- gocnn/gocuStars: 155CPrototype
- dis0rder0x00/stillepostStars: 155CPrototype
- mat-mgm/kb-prologStars: 155CPrototype
- matricks/bamStars: 155CPrototype
- jperfetto/OpenPCRStars: 155CPrototype
- qnikst/kbddStars: 155CPrototype