AlphaUncommon
WangXuan95/FPGA-UART
This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。
- Owner
- WangXuan95 (personal account)
- Stars
- Stars: 354
- Forks
- Forks: 55
- Language
- Verilog
- License
- GPL-3.0
- Created
- 2019
- Topics
- uartverilogrtlfpga
- Tier
- Alpha (250 to 699 ★) What this tier means
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