AlphaUncommon
WangXuan95/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
- Owner
- WangXuan95 (personal account)
- Stars
- Stars: 442
- Forks
- Forks: 81
- Language
- SystemVerilog
- License
- GPL-3.0
- Created
- 2019
- Topics
- riscvrisc-vrv32isocfpgasoftcorertlverilogsystemverilogcpu
- Tier
- Alpha (250 to 699 ★) What this tier means
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