BetaRare
ZipCPU/wb2axip
Bus bridges and other odds and ends
- Owner
- ZipCPU (personal account)
- Stars
- Stars: 713
- Forks
- Forks: 128
- Language
- Verilog
- License
- None
- Created
- 2016
- Topics
- fpgawishbonewishbone-busaxi-busxilinxxilinx-vivadogplv3
- Tier
- Beta (700 to 1,999 ★) What this tier means
More repos by ZipCPU
All 14 repos by ZipCPU- ZipCPU/zipcpuStars: 1,597VerilogBeta
- ZipCPU/sdspiStars: 425VerilogAlpha
- ZipCPU/wbuart32Stars: 356VerilogAlpha
- ZipCPU/eth10gStars: 279CAlpha
- ZipCPU/dblclockfftStars: 269C++Alpha
- ZipCPU/autofpgaStars: 194C++Prototype
Nearby in Verilog
All Verilog repos- alexforencich/verilog-i2cStars: 731VerilogBeta
- antonblanchard/microwattStars: 729VerilogBeta
- OpenTimer/OpenTimerStars: 722VerilogBeta
- jmahler/mips-cpuStars: 660VerilogAlpha
- fguzman82/gateGPTStars: 656VerilogAlpha
- ultraembedded/core_ddr3_controllerStars: 645VerilogAlpha