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AlphaUncommon

ultraembedded/core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

Owner
ultraembedded (personal account)
Stars
Stars: 644
Forks
Forks: 111
Language
Verilog
License
None
Created
2020
Tier
Alpha (250 to 699 ★) What this tier means
View on GitHub

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