PrototypeCommon
ekb0412/100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
- Owner
- ekb0412 (personal account)
- Stars
- Stars: 134
- Forks
- Forks: 17
- Language
- Verilog
- License
- Apache-2.0
- Created
- 2023
- Topics
- digital-system-designasicfpgaxilinx-vivadoverilog-hdlvlsi-design
- Tier
- Prototype (100 to 249 ★) What this tier means
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