PrototypeCommon
eminfedar/fedar-f1-rv64im
5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
- Owner
- eminfedar (personal account)
- Stars
- Stars: 215
- Forks
- Forks: 21
- Language
- Verilog
- License
- MIT
- Created
- 2021
- Topics
- riscv64riscvriscv64imcore
- Tier
- Prototype (100 to 249 ★) What this tier means
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