PrototypeCommon
liuqdev/8-bits-RISC-CPU-Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
- Owner
- liuqdev (personal account)
- Stars
- Stars: 169
- Forks
- Forks: 42
- Language
- Verilog
- License
- MIT
- Created
- 2019
- Topics
- verilogfsmrisccpu
- Tier
- Prototype (100 to 249 ★) What this tier means
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