PrototypeCommon
mirseo/JSilicon
JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.
- Owner
- mirseo (personal account)
- Stars
- Stars: 101
- Forks
- Forks: 10
- Language
- SystemVerilog
- License
- Apache-2.0
- Created
- 2025
- Topics
- aluasicchip-designfinite-state-machinertlrtl-designverilogcontrol-logicdigital-designsopen-source-hardware
- Tier
- Prototype (100 to 249 ★) What this tier means
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