Illustration drawn by RepoMasters from the repo’s ID and its language color. Credits
AlphaUncommon

openhwfoundation/cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Owner
openhwfoundation (organization)
Stars
Stars: 659
Forks
Forks: 591
Language
SystemVerilog
License
None
Created
2021
Tier
Alpha (250 to 699 ★) What this tier means
View on GitHub

More repos by openhwfoundation

All 13 repos by openhwfoundation

Nearby in SystemVerilog

All SystemVerilog repos