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tscheipel/HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practic…

Owner
tscheipel (personal account)
Stars
Stars: 198
Forks
Forks: 106
Language
SystemVerilog
License
MIT
Created
2024
Topics
assembly-programmingc-programmingcomputer-architecturegtkwavehardware-software-codesignmicrocontroller-designopen-educational-resourcespipelinesprocessor-architectureprocessor-design
Tier
Prototype (100 to 249 ★) What this tier means
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