PrototypeCommon
zhanghai/archexp
浙江大学计算机体系结构课程实验
Archived: this repository is read-only
- Owner
- zhanghai (personal account)
- Stars
- Stars: 182
- Forks
- Forks: 27
- Language
- Verilog
- License
- GPL-3.0
- Created
- 2016
- Tier
- Prototype (100 to 249 ★) What this tier means
More repos by zhanghai
All 17 repos by zhanghai- zhanghai/MaterialFilesStars: 9,382KotlinStable
- zhanghai/DouyaStars: 4,531JavaRC
- zhanghai/MaterialProgressBarStars: 2,233JavaRC
- zhanghai/MaterialRatingBarStars: 1,954JavaBeta
- zhanghai/MaterialColdStartStars: 1,213ShellBeta
- zhanghai/AndroidFastScrollStars: 749JavaBeta
Nearby in Verilog
All Verilog repos- thousrm/universal_NPU-CNN_acceleratorStars: 184VerilogPrototype
- ash-olakangal/RISC-V-ProcessorStars: 183VerilogPrototype
- sfmth/OpenSpikeStars: 182VerilogPrototype
- 1801BM1/cpu11Stars: 181VerilogPrototype
- Dazhuzhu-github/systolic-arrayStars: 181VerilogPrototype
- hankshyu/ICLab-2023Stars: 181VerilogPrototype