PrototypeCommon
AngeloJacobo/RISC-V
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
- Owner
- AngeloJacobo (personal account)
- Stars
- Stars: 139
- Forks
- Forks: 11
- Language
- Verilog
- License
- MIT
- Created
- 2022
- Topics
- risc-vverilogrv32irv32cpuriscv5-stage-pipelineformal-verification
- Tier
- Prototype (100 to 249 ★) What this tier means
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