AlphaUncommon
SparcLab/OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
- Owner
- SparcLab (organization)
- Stars
- Stars: 309
- Forks
- Forks: 53
- Language
- Verilog
- License
- GPL-3.0
- Created
- 2020
- Topics
- digitalarchitectureserdesopenlaneskywateropenpdk
- Tier
- Alpha (250 to 699 ★) What this tier means
Nearby in Verilog
All Verilog repos- Modos-Labs/CasterStars: 312VerilogAlpha
- Xilinx/libsystemctlm-socStars: 311VerilogAlpha
- fromgof/TridentVisionStars: 311VerilogAlpha
- budude2/openfpga-GBCStars: 308VerilogAlpha
- damdoy/ice40_ultraplus_examplesStars: 302VerilogAlpha
- efabless/raven-picorv32Stars: 299VerilogAlpha