RCEpic
YosysHQ/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Archived: this repository is read-only
- Owner
- YosysHQ (organization)
- Stars
- Stars: 4,397
- Forks
- Forks: 1,032
- Language
- Verilog
- License
- ISC
- Created
- 2015
- Tier
- RC (2,000 to 4,999 ★) What this tier means
More repos by YosysHQ
All 13 repos by YosysHQ- YosysHQ/yosysStars: 4,863C++RC
- YosysHQ/oss-cad-suite-buildStars: 1,799ShellBeta
- YosysHQ/nextpnrStars: 1,788C++Beta
- YosysHQ/icestormStars: 1,193PythonBeta
- YosysHQ/apiculaStars: 704PythonBeta
- YosysHQ/sbyStars: 561PythonAlpha
Nearby in Verilog
All Verilog repos- The-OpenROAD-Project/OpenROADStars: 3,254VerilogRC
- alexforencich/verilog-ethernetStars: 3,145VerilogRC
- SI-RISCV/e200_opensourceStars: 2,855VerilogRC