RCEpic
alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
- Owner
- alexforencich (personal account)
- Stars
- Stars: 3,145
- Forks
- Forks: 867
- Language
- Verilog
- License
- MIT
- Created
- 2014
- Tier
- RC (2,000 to 4,999 ★) What this tier means
More repos by alexforencich
All 13 repos by alexforencich- alexforencich/verilog-axiStars: 2,168VerilogRC
- alexforencich/verilog-pcieStars: 1,675VerilogBeta
- alexforencich/verilog-axisStars: 925PythonBeta
- alexforencich/verilog-i2cStars: 731VerilogBeta
- alexforencich/verilog-uartStars: 591VerilogAlpha
- alexforencich/cocotbext-axiStars: 368PythonAlpha
Nearby in Verilog
All Verilog repos- YosysHQ/picorv32Stars: 4,397VerilogRC
- The-OpenROAD-Project/OpenROADStars: 3,254VerilogRC
- SI-RISCV/e200_opensourceStars: 2,855VerilogRC
- darklife/darkriscvStars: 2,632VerilogRC
- corundum/corundumStars: 2,505VerilogRC