RCEpic
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
- Owner
- darklife (organization)
- Stars
- Stars: 2,632
- Forks
- Forks: 331
- Language
- Verilog
- License
- BSD-3-Clause
- Created
- 2018
- Topics
- riscvverilogrisc-vfpgacore
- Tier
- RC (2,000 to 4,999 ★) What this tier means
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