Illustration drawn by RepoMasters from the repo’s ID and its language color. Credits
PrototypeCommon

snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM,…

Owner
snbk001 (personal account)
Stars
Stars: 234
Forks
Forks: 40
Language
Verilog
License
None
Created
2022
Topics
verilogtestbenchesverilog-designverilog-codeverilog-hdlverilog-programsverilog-projectself-checking
Tier
Prototype (100 to 249 ★) What this tier means
View on GitHub

Nearby in Verilog

All Verilog repos