Illustration drawn by RepoMasters from the repo’s ID and its language color. Credits
PrototypeCommon

chipsalliance/synlig

SystemVerilog synthesis tool

Owner
chipsalliance (organization)
Stars
Stars: 237
Forks
Forks: 29
Language
Verilog
License
Apache-2.0
Created
2021
Tier
Prototype (100 to 249 ★) What this tier means
View on GitHub

More repos by chipsalliance

All 29 repos by chipsalliance

Nearby in Verilog

All Verilog repos