RCEpic
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
- Owner
- alexforencich (personal account)
- Stars
- Stars: 2,168
- Forks
- Forks: 546
- Language
- Verilog
- License
- MIT
- Created
- 2018
- Tier
- RC (2,000 to 4,999 ★) What this tier means
More repos by alexforencich
All 13 repos by alexforencich- alexforencich/verilog-ethernetStars: 3,145VerilogRC
- alexforencich/verilog-pcieStars: 1,675VerilogBeta
- alexforencich/verilog-axisStars: 925PythonBeta
- alexforencich/verilog-i2cStars: 731VerilogBeta
- alexforencich/verilog-uartStars: 591VerilogAlpha
- alexforencich/cocotbext-axiStars: 368PythonAlpha
Nearby in Verilog
All Verilog repos- corundum/corundumStars: 2,505VerilogRC
- vortexgpgpu/vortexStars: 2,378VerilogRC
- nvdla/hwStars: 2,196VerilogRC
- XUANTIE-RV/wujian100_openStars: 2,032VerilogRC
- pConst/basic_verilogStars: 2,029VerilogRC
- riscv-mcu/e203_hbirdv2Stars: 1,973VerilogBeta