Illustration drawn by RepoMasters from the repo’s ID and its language color. Credits
PrototypeCommon

avakar/usbcorev

A full-speed device-side USB peripheral core written in Verilog.

Owner
avakar (personal account)
Stars
Stars: 244
Forks
Forks: 47
Language
Verilog
License
None
Created
2013
Topics
fpgaverilogusb
Tier
Prototype (100 to 249 ★) What this tier means
View on GitHub

More repos by avakar

All 3 repos by avakar

Nearby in Verilog

All Verilog repos