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PrototypeCommon

chili-chips-ba/openCologne-PCIE

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE conne…

Owner
chili-chips-ba (personal account)
Stars
Stars: 114
Forks
Forks: 14
Language
SystemVerilog
License
BSD-3-Clause
Created
2025
Topics
endpointfpgam2pcbpciepipertlverilogbfmedubos5
Tier
Prototype (100 to 249 ★) What this tier means
View on GitHub

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