PrototypeCommon
spcl/pspin
PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
- Owner
- spcl (organization)
- Stars
- Stars: 108
- Forks
- Forks: 20
- Language
- SystemVerilog
- License
- None
- Created
- 2021
- Topics
- packet-processingin-network-computespinnetworkingpulp
- Tier
- Prototype (100 to 249 ★) What this tier means
More repos by spcl
All 14 repos by spcl- spcl/graph-of-thoughtsStars: 2,851PythonRC
- spcl/daceStars: 598PythonAlpha
- spcl/QuaRotStars: 540PythonAlpha
- spcl/gemm_hlsStars: 394C++Alpha
- spcl/pymlirStars: 269PythonAlpha
- spcl/MRAGStars: 242PythonPrototype
Nearby in SystemVerilog
All SystemVerilog repos- Weiyet/MakerCode_RTLChallengeStars: 109SystemVerilogPrototype
- WangXuan95/UH-JLSStars: 108SystemVerilogPrototype
- chili-chips-ba/openCologneStars: 108SystemVerilogPrototype
- seabeam/yuu_ahbStars: 106SystemVerilogPrototype
- gundy/tiny-synthStars: 105SystemVerilogPrototype