PrototypeCommon
WangXuan95/UH-JLS
An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。
- Owner
- WangXuan95 (personal account)
- Stars
- Stars: 108
- Forks
- Forks: 22
- Language
- SystemVerilog
- License
- GPL-3.0
- Created
- 2021
- Topics
- fpgaimage-compressionimage-encoderjpeg-lsverilog
- Tier
- Prototype (100 to 249 ★) What this tier means
More repos by WangXuan95
All 23 repos by WangXuan95- WangXuan95/FPGA-FOCStars: 994VerilogBeta
- WangXuan95/FPGA-USB-DeviceStars: 934VerilogBeta
- WangXuan95/Xilinx-FPGA-PCIe-XDMA-TutorialStars: 869BatchfileBeta
- WangXuan95/BSV_Tutorial_cnStars: 612BluespecAlpha
- WangXuan95/USTC-RVSoCStars: 442SystemVerilogAlpha
- WangXuan95/FPGA-ftdi245fifoStars: 363VerilogAlpha
Nearby in SystemVerilog
All SystemVerilog repos- Weiyet/MakerCode_RTLChallengeStars: 109SystemVerilogPrototype
- spcl/pspinStars: 108SystemVerilogPrototype
- chili-chips-ba/openCologneStars: 108SystemVerilogPrototype
- seabeam/yuu_ahbStars: 106SystemVerilogPrototype
- gundy/tiny-synthStars: 105SystemVerilogPrototype