BetaRare
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
- Owner
- ultraembedded (personal account)
- Stars
- Stars: 1,811
- Forks
- Forks: 294
- Language
- Verilog
- License
- BSD-3-Clause
- Created
- 2014
- Topics
- risc-vcpuverilogfpgaverilatorrv32imrv32iriscv-linuxpipeline-processorasic
- Tier
- Beta (700 to 1,999 ★) What this tier means
More repos by ultraembedded
All 14 repos by ultraembedded- ultraembedded/biriscvStars: 1,327VerilogBeta
- ultraembedded/coresStars: 939VerilogBeta
- ultraembedded/core_ddr3_controllerStars: 644VerilogAlpha
- ultraembedded/FPGAmpStars: 307CAlpha
- ultraembedded/core_jpegStars: 283VerilogAlpha
- ultraembedded/riscv_socStars: 212VerilogPrototype
Nearby in Verilog
All Verilog repos- riscv-mcu/e203_hbirdv2Stars: 1,967VerilogBeta
- olofk/servStars: 1,912VerilogBeta
- ufrisk/pcileech-fpgaStars: 1,848VerilogBeta
- alexforencich/verilog-pcieStars: 1,675VerilogBeta
- ZipCPU/zipcpuStars: 1,597VerilogBeta
- XUANTIE-RV/openc910Stars: 1,490VerilogBeta