SystemVerilog GitHub repos, page 3
155 SystemVerilog repos in the catalog, most starred first.
- pulp-platform/snitchStars: 229SystemVerilogPrototype
- svunit/svunitStars: 227SystemVerilogPrototype
- subbdue/systemverilog.ioStars: 226SystemVerilogPrototype
- agg23/openfpga-NESStars: 224SystemVerilogPrototype
- taichi-ishitani/tnocStars: 216SystemVerilogPrototype
- tilk/riscv-simple-svStars: 216SystemVerilogPrototype
- openhwfoundation/core-v-mcuStars: 215SystemVerilogPrototype
- cluelogic/uvm-tutorial-for-candy-loversStars: 211SystemVerilogPrototype
- ClusterM/coolgirl-famicom-multicartStars: 210SystemVerilogPrototype
- eevaain/tiny-tpu-oldStars: 206SystemVerilogPrototype
- MiSTer-devel/NES_MiSTerStars: 205SystemVerilogPrototype
- FeSens/auto-arch-tournamentStars: 205SystemVerilogPrototype
- courageheart/AMBA_APB_SRAMStars: 203SystemVerilogPrototype
- aignacio/ravenocStars: 201SystemVerilogPrototype
- yuri-panchul/systemverilog-homeworkStars: 199SystemVerilogPrototype
- tscheipel/HaDes-VStars: 198SystemVerilogPrototype
- azonenberg/starshipraiderStars: 193SystemVerilogPrototype
- nand2mario/z386Stars: 192SystemVerilogPrototype
- PacktPublishing/The-FPGA-Programming-Handbook-Second-EditionStars: 191SystemVerilogPrototype
- karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2Stars: 187SystemVerilogPrototype
- kumarrishav14/AXIStars: 187SystemVerilogPrototype
- Xilinx/RecoNICStars: 181SystemVerilogPrototype
- agg23/fpga-tamagotchiStars: 178SystemVerilogPrototype
- kilmu1337/VGK-DMA-BYPASSStars: 178SystemVerilogPrototype
- ijor/fx68kStars: 174SystemVerilogPrototype
- mbits-mirafra/SystemVerilogCourseStars: 173SystemVerilogPrototype
- zeroasiccorp/umiStars: 172SystemVerilogPrototype
- mayurkubavat/UVM-ExamplesStars: 169SystemVerilogPrototype
- riscv-verification/RVVIStars: 168SystemVerilogPrototype
- bsc-loca/sargantanaStars: 168SystemVerilogPrototype