SystemVerilog GitHub repos, page 4
157 SystemVerilog repos in the catalog, most starred first.
- munetomo-maruyama/mmRISC-2Stars: 167SystemVerilogPrototype
- srg320/Saturn_MiSTerStars: 166SystemVerilogPrototype
- gnodipac886/ViT-FPGA-TPUStars: 165SystemVerilogPrototype
- GodelMachine/AHB2Stars: 164SystemVerilogPrototype
- openhwfoundation/cv32e40sStars: 163SystemVerilogPrototype
- Xilinx/open-nic-shellStars: 161SystemVerilogPrototype
- iammituraj/pequeno_riscvStars: 161SystemVerilogPrototype
- chenyuliu577-cyber/jyd-rv32i-fpga-coreStars: 161SystemVerilogPrototype
- agalimberti/NoCRouterStars: 160SystemVerilogPrototype
- chipsalliance/caliptra-rtlStars: 160SystemVerilogPrototype
- accellera-official/uvm-coreStars: 156SystemVerilogPrototype
- Dollbar/OverflowStars: 154SystemVerilogPrototype
- dshekhalev/FECStars: 153SystemVerilogPrototype
- waviousllc/wav-lpddr-hwStars: 148SystemVerilogPrototype
- WangXuan95/FPGA-SATA-HBAStars: 148SystemVerilogPrototype
- ic-lab-duth/RISC-V-VectorStars: 147SystemVerilogPrototype
- amd/mini-ispStars: 147SystemVerilogPrototype
- zeroasiccorp/wildebeestStars: 146SystemVerilogPrototype
- chipsalliance/uvm-verilatorStars: 143SystemVerilogPrototype
- pulp-platform/register_interfaceStars: 141SystemVerilogPrototype
- marcoz001/axi-uvmStars: 140SystemVerilogPrototype
- openhwfoundation/cva5Stars: 140SystemVerilogPrototype
- MiSTer-devel/C64_MiSTerStars: 139SystemVerilogPrototype
- microsoft/cheriot-ibexStars: 138SystemVerilogPrototype
- ZcashFoundation/zcash-fpgaStars: 135SystemVerilogPrototype
- lizhirui/AXI-SDCard-High-Speed-ControllerStars: 131SystemVerilogPrototype
- KastnerRG/cgra4mlStars: 129SystemVerilogPrototype
- agg23/analogue-pocket-utilsStars: 127SystemVerilogPrototype
- krikzz/edn8-pro-pubStars: 126SystemVerilogPrototype
- pulp-platform/redmuleStars: 126SystemVerilogPrototype