PrototypeCommon
chenyuliu577-cyber/jyd-rv32i-fpga-core
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
- Owner
- chenyuliu577-cyber (personal account)
- Stars
- Stars: 155
- Forks
- Forks: 32
- Language
- SystemVerilog
- License
- MIT
- Created
- 2026
- Topics
- computer-architecturecontestcpudigital-designeducationfpgahardware-designriscvrv32isystemverilog
- Tier
- Prototype (100 to 249 ★) What this tier means
Nearby in SystemVerilog
All SystemVerilog repos- agalimberti/NoCRouterStars: 160SystemVerilogPrototype
- chipsalliance/caliptra-rtlStars: 160SystemVerilogPrototype
- accellera-official/uvm-coreStars: 156SystemVerilogPrototype
- dshekhalev/FECStars: 153SystemVerilogPrototype
- Dollbar/OverflowStars: 153SystemVerilogPrototype
- waviousllc/wav-lpddr-hwStars: 148SystemVerilogPrototype