BetaRare
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
- Owner
- chipsalliance (organization)
- Stars
- Stars: 1,974
- Forks
- Forks: 314
- Language
- C++
- License
- None
- Created
- 2019
- Topics
- systemveriloglexeryaccsyntax-treelinterformatterparsersystemverilog-parserstyle-linterhacktoberfest
- Tier
- Beta (700 to 1,999 ★) What this tier means
More repos by chipsalliance
All 29 repos by chipsalliance- chipsalliance/chiselStars: 4,827ScalaRC
- chipsalliance/rocket-chipStars: 3,895ScalaRC
- chipsalliance/riscv-dvStars: 1,375PythonBeta
- chipsalliance/Cores-VeeR-EH1Stars: 971SystemVerilogBeta
- chipsalliance/firrtlStars: 748ScalaBeta
- chipsalliance/chisel-templateStars: 709ShellBeta
Nearby in C++
All C++ repos- patrikhuber/eosStars: 1,982C++Beta
- numworks/epsilonStars: 1,979C++Beta
- rlguy/Blender-FLIP-FluidsStars: 1,974C++Beta
- NVIDIA-Omniverse/usd-brepStars: 1,973C++Beta
- logcabin/logcabinStars: 1,972C++Beta
- facebookincubator/spectrumStars: 1,971C++Beta