GitHub repos by chipsalliance
29 public repos by chipsalliance in the catalog, most starred first.
- chipsalliance/chiselStars: 4,826ScalaRC
- chipsalliance/rocket-chipStars: 3,896ScalaRC
- chipsalliance/veribleStars: 1,973C++Beta
- chipsalliance/riscv-dvStars: 1,375PythonBeta
- chipsalliance/Cores-VeeR-EH1Stars: 971SystemVerilogBeta
- chipsalliance/firrtlStars: 748ScalaBeta
- chipsalliance/chisel-templateStars: 710ShellBeta
- chipsalliance/CaliptraStars: 485Alpha
- chipsalliance/SurelogStars: 476C++Alpha
- chipsalliance/f4pgaStars: 453PythonAlpha
- chipsalliance/sv-testsStars: 406SystemVerilogAlpha
- chipsalliance/Cores-VeeR-EL2Stars: 349SystemVerilogAlpha
- chipsalliance/VeeRwolfStars: 343VerilogAlpha
- chipsalliance/t1Stars: 324ScalaAlpha
- chipsalliance/f4pga-examplesStars: 290VerilogAlpha
- chipsalliance/Cores-VeeR-EH2Stars: 282SystemVerilogAlpha
- chipsalliance/UHDMStars: 269C++Alpha
- chipsalliance/dromajoStars: 244C++Prototype
- chipsalliance/synligStars: 237VerilogPrototype
- chipsalliance/silicon-notebooksStars: 178Jupyter NotebookPrototype
- chipsalliance/caliptra-swStars: 172RustPrototype
- chipsalliance/caliptra-rtlStars: 160SystemVerilogPrototype
- chipsalliance/VeeR-ISSStars: 158C++Prototype
- chipsalliance/treadleStars: 157ScalaPrototype
- chipsalliance/aib-phy-hardwareStars: 151VerilogPrototype
- chipsalliance/uvm-verilatorStars: 142SystemVerilogPrototype
- chipsalliance/riscv-vector-testsStars: 118GoPrototype
- chipsalliance/fpga-tool-perfStars: 108PythonPrototype
- chipsalliance/fasmStars: 103PythonPrototype