PrototypeCommon
ultraembedded/openlogicbit
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
- Owner
- ultraembedded (personal account)
- Stars
- Stars: 178
- Forks
- Forks: 24
- Language
- Verilog
- License
- Apache-2.0
- Created
- 2021
- Topics
- fpgalogic-analyzerxilinx-fpgalattice-fpgaaltera-fpgaftdi232hftdi2232hdigital-signal-analyzerverilog
- Tier
- Prototype (100 to 249 ★) What this tier means
More repos by ultraembedded
All 14 repos by ultraembedded- ultraembedded/riscvStars: 1,811VerilogBeta
- ultraembedded/biriscvStars: 1,327VerilogBeta
- ultraembedded/coresStars: 939VerilogBeta
- ultraembedded/core_ddr3_controllerStars: 644VerilogAlpha
- ultraembedded/FPGAmpStars: 307CAlpha
- ultraembedded/core_jpegStars: 283VerilogAlpha
Nearby in Verilog
All Verilog repos- nanamake/r22sdfStars: 179VerilogPrototype
- lamda-bbo/Open3DBenchStars: 179VerilogPrototype
- denandz/lpc_sniffer_tpmStars: 178VerilogPrototype
- DreamSourceLab/DSLogic-hdlStars: 177VerilogPrototype
- mustafabbas/ECE1373_2016_hft_on_fpgaStars: 176VerilogPrototype
- MiSTer-devel/NeoGeo_MiSTerStars: 176VerilogPrototype