PrototypeCommon
chipsalliance/aib-phy-hardware
Advanced Interface Bus (AIB) die-to-die hardware open source
- Owner
- chipsalliance (organization)
- Stars
- Stars: 151
- Forks
- Forks: 39
- Language
- Verilog
- License
- Apache-2.0
- Created
- 2020
- Tier
- Prototype (100 to 249 ★) What this tier means
More repos by chipsalliance
All 29 repos by chipsalliance- chipsalliance/chiselStars: 4,826ScalaRC
- chipsalliance/rocket-chipStars: 3,895ScalaRC
- chipsalliance/veribleStars: 1,974C++Beta
- chipsalliance/riscv-dvStars: 1,375PythonBeta
- chipsalliance/Cores-VeeR-EH1Stars: 971SystemVerilogBeta
- chipsalliance/firrtlStars: 748ScalaBeta
Nearby in Verilog
All Verilog repos- CutestPanda/OpensocStars: 152VerilogPrototype
- freecores/verilog_fixed_point_math_libraryStars: 151VerilogPrototype
- SocialistDalao/UltraMIPS_NSCSCCStars: 151VerilogPrototype
- lucky-wfw/ARM_AMBA_DesignStars: 150VerilogPrototype
- michaelehab/AES-VerilogStars: 149VerilogPrototype