PrototypeCommon
openhwfoundation/cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40P
- Owner
- openhwfoundation (organization)
- Stars
- Stars: 163
- Forks
- Forks: 29
- Language
- SystemVerilog
- License
- None
- Created
- 2021
- Tier
- Prototype (100 to 249 ★) What this tier means
More repos by openhwfoundation
All 13 repos by openhwfoundation- openhwfoundation/cva6Stars: 3,183AssemblyRC
- openhwfoundation/cv32e40pStars: 1,317SystemVerilogBeta
- openhwfoundation/core-v-verifStars: 737AssemblyBeta
- openhwfoundation/cvwStars: 659SystemVerilogAlpha
- openhwfoundation/cvfpuStars: 648SystemVerilogAlpha
- openhwfoundation/core-v-coresStars: 380Alpha
Nearby in SystemVerilog
All SystemVerilog repos- srg320/Saturn_MiSTerStars: 166SystemVerilogPrototype
- gnodipac886/ViT-FPGA-TPUStars: 165SystemVerilogPrototype
- GodelMachine/AHB2Stars: 164SystemVerilogPrototype
- Xilinx/open-nic-shellStars: 161SystemVerilogPrototype
- iammituraj/pequeno_riscvStars: 161SystemVerilogPrototype
- chenyuliu577-cyber/jyd-rv32i-fpga-coreStars: 161SystemVerilogPrototype