SystemVerilog GitHub repos, page 5
157 SystemVerilog repos in the catalog, most starred first.
- bsc-loca/sauriaStars: 125SystemVerilogPrototype
- nelsoncsc/ISP_UVMStars: 124SystemVerilogPrototype
- lowRISC/muntjacStars: 124SystemVerilogPrototype
- openhwfoundation/cv-hpdcacheStars: 124SystemVerilogPrototype
- meiniKi/FazyRVStars: 124SystemVerilogPrototype
- pulp-platform/pulp_clusterStars: 123SystemVerilogPrototype
- RC4ML/ShuhaiStars: 123SystemVerilogPrototype
- zero-day-labs/riscv-iommuStars: 122SystemVerilogPrototype
- daglem/reDIP-SIDStars: 121SystemVerilogPrototype
- Siddhi-95/AHB-to-APB-Bridge-VerificationStars: 121SystemVerilogPrototype
- krikzz/mega-ed-pubStars: 120SystemVerilogPrototype
- StefanSredojevic/Deep-Neural-Network-Hardware-AcceleratorStars: 117SystemVerilogPrototype
- chili-chips-ba/openCologne-PCIEStars: 116SystemVerilogPrototype
- chili-chips-ba/openPCIEStars: 114SystemVerilogPrototype
- nand2mario/z8086Stars: 114SystemVerilogPrototype
- pulp-platform/heroStars: 113SystemVerilogPrototype
- mole99/greyhound-ihpStars: 112SystemVerilogPrototype
- Verdvana/AXI4_InterconnectStars: 111SystemVerilogPrototype
- ttchisholm/10g-low-latency-ethernetStars: 111SystemVerilogPrototype
- RoaLogic/ahb3lite_interconnectStars: 110SystemVerilogPrototype
- trivialmips/TrivialMIPSStars: 110SystemVerilogPrototype
- eliaskousk/parallella-riscvStars: 109SystemVerilogPrototype
- mmxsrup/axi4-interfaceStars: 109SystemVerilogPrototype
- Weiyet/MakerCode_RTLChallengeStars: 109SystemVerilogPrototype
- spcl/pspinStars: 108SystemVerilogPrototype
- WangXuan95/UH-JLSStars: 108SystemVerilogPrototype
- chili-chips-ba/openCologneStars: 108SystemVerilogPrototype
- seabeam/yuu_ahbStars: 106SystemVerilogPrototype
- gundy/tiny-synthStars: 105SystemVerilogPrototype
- OPAE/intel-fpga-bbbStars: 104SystemVerilogPrototype